In many applications, including clock recovery applications, it is often necessary to compare and control the phase of one or more clock signals. For example, in one common type of analog Clock and Data Recovery system (CDR), the phase of the input data is compared to the phase of two or more sampling clocks. The sampling clocks may be generated, for example, from a fixed reference clock by a Delay-Locked-Loop (DLL). A DLL is a control loop, separate from the primary CDR control loop, that acts to control the spacing between the sampling clocks. The DLL develops a set of phases that are “selected” and interpolated by the CDR control loop to obtain the correct phase required to match-up with the incoming data transition phase.
Typically, a phase detector in the DLL determines the phase difference between adjacent rising edges of two delayed clock signals. If the phase detector detects a phase lag between the rising edges, the phase detector generates a downward control signal, indicating an extent of the phase lag. Likewise, if the phase detector detects a phase lead between the rising edges, the phase detector generates an upward control signal, indicating an extent of the phase lead. The upward and downward control signals are typically applied to a charge pump that generates a positive or negative current pulse having a pulse width that is proportional to the phase difference. Thereafter, the current pulse generated by the charge pump is typically integrated by a loop filter, such as a capacitor. The capacitor voltage is then applied to the bias voltage generator which provides the VCDL control voltages. The VCDL control voltages then change to raise or lower the delay of each delay cell within the VCDL.
While such DLL circuits effectively generate the sampling clocks, they suffer from a number of limitations, which if overcome, could further improve the utility and accuracy of such DLLs. For example, when the DLLs are implemented using integrated circuit technology, and the phase detector is implemented as a D-type flip flop, a set-up/hold time offset is introduced into the phase difference detection.
U.S. patent application Ser. No. 11/020,022, entitled, “Trimming Method and Apparatus for Voltage Controlled Delay Loop with Central Interpolator,” discloses methods and apparatus for trimming a desired delay element in a voltage controlled delay loop (ensures that the delay provided by each delay element in the VCDL loop are the same). U.S. patent application Ser. No. 11/141,703, entitled, “Parallel Trimming Method and Apparatus for a Voltage Controlled Delay Loop,” discloses a parallel trimming method and apparatus for a voltage controlled delay loop (trims the latch buffer associated with each delay element).
A need exists for a trimming method and apparatus for a phase detector in a DLL. A further need exists for a method and apparatus for trimming a phase offset in a phase detector of a DLL to approximately zero.